Many high performance computing systems include a scan operating mode for use in system initialization, error diagnosis and error reporting. During such a scan mode, all the storage elements, such as the pipeline registers and programmable delays, of a given section of circuitry are coupled together, into a scan loop. Typically, the loop is established using multiplexers operable during the normal operating mode to maintain the interconnection of storage and logic elements required for normal processing and during the scan mode switch to connect the storage elements directly together in a loop to the exclusion of the logic elements. Once the scan loop is established during the scan mode, a scan serial pattern of data can be clocked through the loop such that each storage element can be set to a logic one or a logic zero as desired. It should be noted that these scan loops can vary in size and complexity depending on the application; some scan loops may only consist of a few storage elements while other scan loops may consist of a thousand or more storage elements.
The ability to set each storage element in the scan loop to a given logic state has several important advantages. For example, by using the scan mode during system initialization, the registers and variable delay components in the loop can be set to their initial values. Further, during system diagnosis, a test data pattern can be clocked into the storage elements of the scan loop during the scan mode. The system is then reconfigured for the normal processing mode and the test data clocked from storage element to storage element through the intervening logic circuitry. After the normal mode clocking, the shifted data can then be read out by returning to the scan mode and then tested to determine where any errors, if any, are occurring. Finally, the scan mode can be used for error reporting. In this case, the scan loop or a subset of the scan loop is used to hold data when an error is detected until the data can be scanned out by a controller.
Many times a substantial problem arises when scan loops are being designed from storage elements of differing maximum operating speeds. This situation may occur for example when the various storage elements to be included in a given scan loop have been fabricated from more that one fabrication technology (i.e., ECL, TTL, CMOS, BiCMOS). At least two techniques have been used in the prior art to handle such mismatches in operating performance. In the first technique, in order to maintain proper data flow through the slowest elements, a single clock with a clock speed no greater than the maximum allowable clock speed for the slowest elements is used to drive all the elements of the loop. This method has the substantial disadvantage of slowing down the entire scan loop. Further, if the clock being used to drive the scan circuit in the scan mode that differs from that being used in the normal processing mode, additional clock generation circuitry is required which further complicates the design. The second prior art approach to driving scan loop elements of varying maximum operating speeds is to use different clocks commensurate with the speed of the different elements. This method also has serious disadvantages. Additional and/or more complicated clock generation is required to generate all the clocks necessary. Further, the overall timing for the scan loop becomes complex.
Thus, the need has arisen for circuits, systems and methods which allow for efficient establishment of scan loops from storage elements of varying maximum clock speeds. Such circuits, systems and methods should eliminate the need for complex clock generation circuitry while at the same time maintaining maximum performance out of the scan loop circuitry. Further, such circuits, systems and methods should be implemented using a minimal number of components and should be applicable to both board and chip level designs.